Synopsys FY2026: Behind the Chip Designers

Executive Summary

We initiate coverage of Synopsys with a BUY rating and a USD604 target price, representing 50% upside. Synopsys is one of the world’s two dominant EDA vendors, with its tools embedded across many leading edge semiconductor and custom silicon design flows. Its leadership in EDA, broad IP portfolio and acquisition of Ansys position the company to capture a larger share of engineering spending as chip and system complexity rises.

Our BUY call rests on three earnings drivers. First, rising design complexity should increase Core EDA spending per programme through broader tool adoption, higher compute utilisation and growing demand for hardware assisted verification. Second, Design IP is recovering as Synopsys concentrates resources on connectivity, memory and customised IP, while Factory Two strategy pivot serves as an catalyst for further upside by allowing Synopsys to earn development and usage fees, with potential royalties once customer chips enter production. Third, Ansys expands Synopsys into the approximately USD 10 billion simulation and analysis market while creating cross selling opportunities across semiconductor and broader engineering customers.

We believe earnings should grow faster than revenue as operating margins recover and debt is repaid. At the same time, stronger Design IP licensing and accelerating Ansys cost synergies should improve operating leverage.

Current valuation continues to reflect concerns over Design IP execution, China restrictions and Ansys integration, despite improving operating performance. Our forecasts assume low teens revenue growth beyond the FY2026 acquisition step up, as well as margin expansion. Applying a 29x P/E to our FY2028E adjusted EPS of USD20.83, we derive a target price of USD604, represents a 50% upside potential.

Business Overview

Synopsys is a leading provider of electronic design automation (EDA) software, semiconductor intellectual property (IP), and simulation and analysis solutions. Its EDA tools are used to design, verify and prepare semiconductors for manufacturing, while its Design IP business provides reusable, silicon-proven building blocks that customers can integrate directly into their chip designs.

Within EDA, Synopsys operates in a highly concentrated market alongside Cadence and Siemens, with the three vendors controlling more than 85% of the industry. Today, Synopsys holds approximately 39% market share, with particularly strong positions in digital design, synthesis and timing signoff, placing Synopsys within the core design infrastructure of leading semiconductor and electronics companies.

Meanwhile, following the acquisition of Ansys in July 2025, Synopsys expanded beyond semiconductor design into multiphysics and system-level simulation, with its combined portfolio now spans a wider engineering workflow, from designing the chip and integrating semiconductor IP to analysing how the chip, package and surrounding system perform together. The Ansys portfolio has also broadened Synopsys’s reach into automotive, aerospace, industrial and other engineering markets, while deepening its relevance to hyperscalers and systems companies developing increasingly complex advanced nodes.

Revenue Composition and Product Portfolio

In FY2025, EDA contributed 61.9% of Synopsys’s revenue, followed by Ansys at 10.7% and Design IP at 24.8%.  EDA remains the core business. Its tools support chip design, verification and signoff, and are typically sold through two to three years technology subscription licences, namely, ELA (Enterprise License Agreement). This gives Synopsys a recurring revenue base that grows as customers deploy more tools and computing capacity across increasingly complex designs.

Meanwhile, Design IP supplies silicon proven building blocks incorporated into customers’ chips. Following this year’s sale of its Processor IP Solutions business to GlobalFoundries, the portfolio is now focusing on interface, foundation and security IP, including PCIe, UCIe, DDR and HBM. In contrast to the other business segment, Design IP revenue is more dependent on customer design starts, licensing activity and eventual chip production. While this creates greater volatility, it provides direct exposure to custom silicon activity and meaningful operating leverage when utilisation recovers.

Lastly, Ansys adds thermal, electromagnetic, structural and fluid simulation. Its relevance lies in bringing system-level constraints into the chip design process as multi-die and advanced packaging architectures become more prevalent.

Figure 1: Synopsys FY2025 revenue breakdown.

FY2025 Financial Performance

FY2025 was a rather difficult year for Synopsys. While the Ansys acquisition lifted reported revenue 15% to USD7.05 billion, Synopsys’s organic growth at only around 3%. Beneath that headline, EDA continued to grow 7%, while Design IP revenue declined -8% as China restrictions, delays around Intel’s foundry roadmap and gaps in Synopsys’s own IP portfolio pushed out customer licensing activity, pulling the operating margin to 37.3% from 38.5% which translate into lower earnings. That said, we believe the underperformance was mainly driven by Design IP earnings setback, rather than a weakening Synopsys’s core EDA business.

The 1H FY2026 started to see recovery, in which EDA revenue rose 10.2% to USD2.26 billion as customers increased spending on advanced node projects and hardware assisted verification. At the same time, Design IP revenue rose 12% sequentially in 2Q to USD454 million, and its segment margin improved further to 24.4% from 16.2% in 1Q. Together with Ansys synergies and tighter cost control, operating margin improved to 39.5% in 2Q, and the company has restarted capital returns through greater share repurchases activity, which gives us greater confidence that the post-Ansys earnings transition is moving in the right direction.

On top of that, management’s FY2026 guidance remains solid. Despite the revenue revision itself is not significant, management guided a 50bps increase in operating margin to around 41%, alongside a stronger free cash flow guidance to approximately USD2.0 billion. With debt has now reduced lower shortly after the acquisition, we believe lower interest expense should started to support EPS moving into FY27. That said, we expect FY2026 earnings to continue leading by stronger EDA growth and further Ansys cost synergies, with a sustained improvement in Design IP adding further upside.

Table 1: Key financial highlights.

USD millions	FY2025	FY2024	YoY Growth
EDA Revenue	4,369.7	4,071.5	+7.3%
Ansys Revenue	756.6	—	n.m.
Design IP Revenue	1,751.8	1,906.3	–8.1%
Total Revenue	7,054.2	6,127.4	+15.1%
Gross Profit	5,430.4	4,882.4	+11.2%
Operating Income	2,632.9	2,362.1	+11.5%
Operating Margin (%)	37.3%	38.5%	–120 bps
Net Income	2,139.6	2,057.9	+4.0%
Diluted EPS (USD)	12.91	13.20	–2.2%
Free Cash Flow	1,549.2	1,407.3	+10.1%
Source: Synopsys, iFAST compilations. Data as of 31 October 2025.

Industry Overview: EDA

The EDA industry is often overlooked given its relatively small size relative to fabless, foundry and memory players. Yet, the broader EDA and semiconductor IP market, estimated at around USD24 billion (vs broader semiconductor industry that is valued at USD775 billion in 2024), remains central to semiconductor development because every advanced chip must pass through design, verification and signoff before reaching production.

Accordingly, the market is highly concentrated, with Synopsys, Cadence and Siemens controlling more than 85% of industry revenue, giving EDA a level of resilience and pricing power that is not immediately apparent from its market size.

The appeal of EDA lies in the fact that demand is driven less by semiconductor shipments than by the work required to design the next generation of chips. For instance, while chipmakers can reduce production during a downturn, it cannot easily defer a leading edge programme without affecting its future roadmap. At the same time, transitions to advanced nodes, chiplet architectures and more demanding verification flows raise the software and compute required for each tape out, where the EDA and semiconductor IP market has compounded at roughly 13% over the past decade, ahead of the 7% growth in semiconductor R&D.

Moving forward, we expect EDA spending to continue outgrowing the broader semiconductor market as customers undertake more chip programmes and each design becomes more complex. Meanwhile, R&D spending among the top 20 semiconductor companies is expected to rise by 23% in 2026, well above the long-term average of 10%, as AI accelerators, multi-chip architectures and advanced packaging require more design, verification and simulation work. At the same time, customer base is also widening as hyperscalers develop custom silicon alongside traditional fabless companies and IDMs, with systems companies now accounting for around 45% of EDA demand. As such, we believe EDA vendors will benefit from both a broader pool of chip programmes and greater engineering requirements for each project.

Figure 2: Electronic design automation, IP market share.

Source: Bloomberg Intelligence, IDC, iFAST compilations.

Figure 3: R&D spending for top 20 semi device companies.

Source: Bloomberg Intelligence, iFAST compilations.

The Trio Oligopoly

For EDA players, this higher design intensity generally translates into revenue through existing customer relationships, in which large customers typically commit to broad tool portfolios through multi-year Enterprise Licence Agreements (ELAs), and subsequently add token and compute capacity as workloads expand.

Therefore, as EDA retention rate stays above 95% and contractual price escalators of around 3–7% in some agreements, these could provide the recurring revenue base to EDA players, while higher utilisation, wider tool adoption and new node transitions then lift spending within the same account.

Meanwhile, leading chip designers typically use tools from several EDA vendors rather than rely on one end-to-end platform. Among the trio oligopoly, Synopsys is strongest in the digital path to tape-out, particularly in synthesis, digital implementation, timing signoff and verification, with SemiAnalysis estimates that Design Compiler holds around 84–85% share in synthesis, while PrimeTime exceeds 90% in timing signoff. In contrast, Cadence is stronger in custom and analogue design and remains a leading supplier of hardware emulation, while Siemens is deeply entrenched in physical verification through Calibre. This shows that even EDA market remains highly concentrated, it is not a winner-take-all by company, where leadership is tool-specific, and customers use qualified flows from multiple vendors.

Table 2: Tool-level market share (advanced nodes, 7nm and below)

Tool Category	#1 Vendor	Share	#2 Vendor	Share	Others
RTL Synthesis	Synopsys (Design Compiler)	84–85%	Cadence (Genus)	12–15%	<3%
Place & Route	Synopsys (Fusion Compiler)	55–60%	Cadence (Innovus)	35–40%	<5%
Timing Signoff	Synopsys (PrimeTime)	90%+	Cadence (Tempus)	5–8%	<2%
Parasitic Extraction	Synopsys (StarRC)	70–75%	Cadence (Quantus)	20–25%	<5%
Physical Verification	Siemens (Calibre)	85%+	Synopsys (IC Validator)	10–12%	<3%
Functional Simulation	Synopsys (VCS)	45–50%	Cadence (Xcelium)	40–45%	<10%
Hardware Emulation	Cadence (Palladium)	55–60%	Synopsys (ZeBu)	35–40%	<5%
Analog/Custom	Cadence (Virtuoso)	80%+	Synopsys (Custom Compiler)	10–15%	<5%
Formal Verification	Synopsys (VC Formal)	45–50%	Cadence (JasperGold)	40–45%	<10%
Source: SemiAnalysis, iFAST compilations. Data as of 22 May 2026.

Open source AI threat is limited

While the recent AI developments have reopened the debate over whether agents could displace parts of the EDA workflow, particularly after the Kimi K3 demonstration, we note that Kimi operated on an academic 45nm node using open source tools, with the agent coordinating the design process rather than replacing the underlying design, verification and physical solvers. This remains materially different from a leading-edge production flow, where foundry qualified PDK (Process Design Kit) integration, signoff accuracy and design-to-silicon correlation determine whether a chip can be taped out reliably.

Hence, while open source tools become more relevant at mature nodes and in selected parts of the workflow, we do not expect them to displace commercial EDA at the leading-edge node workflow. Instead, the shortage of experienced design engineers should accelerate the adoption of AI-assisted workflows, as customers seek to complete more design work without increasing headcount proportionately.

Figure 4: Semiconductor design engineers remain in shortage. 

Figure 5: EDA sales per user are increasing. 

Figure 6: AI-assisted EDA tools is expected to increase EDA productivity.

Source Bloomberg Intelligence, iFAST compilations.

Investment Theses:

Rising chip complexity expands Synopsys’s EDA spend per design

Core EDA remains Synopsys’s most dependable earnings driver. As advanced designs grow in transistor count and complexity, engineers require broader design, verification and signoff coverage, as well as greater compute capacity, to reach tape out. Given that Synopsys has a rather stronger market positions in verification, signoff, and iterations (as can be seen in Table 2), this would allow Synopsys to increase EDA spend per programme through greater tool penetration and utilisation within existing customer relationships.

To break it further, Synopsys’s EDA software is expected to capture most of the earnings upside, as wider deployment of an established platform carries attractive incremental margins. Meanwhile, Synopsys AI-enabled tools are already increasing contract value where earlier disclosures showed that DSO.ai adopters generated around a 20% uplift to annual contract value, and management is seeing early contract uplift from GPU-accelerated EDA. With these AI-embedded tools, customers can now pay for better power, performance and area (PPA) outcomes, faster turnaround and the ability to run more optimisation, simulation and verification cycles within the same development schedule.

On top of that, while AgentEngineer (Synopsys's platform of AI agents that carry out chip design and verification tasks with limited human supervision) is still in early phase, with commercial adoption and pricing remain at an early stage, it serves as the further upside catalyst, with company disclosed about 20 customers evaluating more than 25 specialised agents across design and verification workflows.

On the other hand, as chips become larger and more complex (SoCs and multi-die systems increase in gate count), testing the entire design through software simulation alone could take longer. Engineers therefore use hardware EDA tools such as ZeBu emulation runs the design on dedicated hardware, while HAPS (High-performance ASIC Prototyping System) prototyping allows software to be developed and tested before first silicon is manufactured. More complex designs therefore require larger systems and greater verification capacity and increase hardware demand per programme.

Recent quarterly performance reinforces our view, with EDA revenue grew slightly above 8% y/y in 2QFY26, while Synopsys secured more than 30 advanced node full flow wins and supported the tape out of an advanced AI accelerator through its integrated 3DIC design to signoff flow. Hence, by embedding Synopsys across more stages of implementation, verification and signoff, we believe these would create further opportunities to monetise from software and compute capacity when customers expand or renew their multi-year contracts. We therefore forecast core EDA growth of 10% annually through FY2029, supported by the approximately 20% contract uplift disclosed for DSO.ai adopters. 

Figure 7: Below showing the complete chip design flow. Increases in chip complexity would increase verification, signoff, and iterations (areas where Synopsys has its strongest market positions). 

Source: SemiAnalysis, iFAST compilations.

Figure 8: Advanced design costs are increasing as increasing complexity.

Source: Bloomberg Intelligence, iFAST compilations.

Figure 9: Core EDA revenue is expected to grow higher from rising advanced node design.  

Figure 10: EDA market size from AI monetisation (supply side) 

Source: SemiAnalysis, iFAST compilations. Data as of 22 May 2026.

Figure 11: software DSO.ai has seen annual contract value uplifting.

Figure 12: Modular hardware-assisted verification architecture supports scalable emulation and FPGA prototyping.

Source: Synopsys.

Design IP is moving up the value chain

While Design IP was the main dragger in FY2025, with both revenue and operating margin declining, the business is now being repositioned towards higher value interface, foundation and customised IP. With that, the company has shifted its focus towards deeper hyperscaler engagements, while IP Accelerated extends Synopsys beyond individual IP blocks into pre-verified subsystems, hardening, signal and power integrity analysis, and silicon bring-up support (the process of powering on a brand-new computer chip for the very first time to see if it works.) With that, we believe this can broaden Synopsys’s IP offerings while reducing its reliance on competing for individual IP blocks based on specifications and price.

In fact, the recent 2Q FY26 financial results shown that licensing recovery is translating into operating leverage, with revenue rose 12% q/q and operating margin improved to 24.4% from 16.2% in 1Q. The uplift was because much of the engineering cost is incurred upfront to develop, while subsequent licences carry comparatively low incremental costs, hence, as licensing activity improves, we expect there will be a larger share of incremental revenue to flow through to operating profit, supporting the margin recovery.

Meanwhile, the shift in Design IP strategy is particularly relevant for hyperscalers developing their own proprietary silicon, where customised connectivity, memory and subsystem IP require closer engineering collaboration. Several IP pipelines that are building now further reinforce our view, including 18 new PCIe 7.0 licences secured in 2QFY26 at a win rate above 90%, more than 150 lifetime UCIe wins, and memory-IP design wins across hyperscalers, AI start-ups and leading semiconductor companies.

Nonetheless, we see further potential upside coming from the “Factory Two“ strategy, a separate customised IP model alongside the traditional build once, license many business, moving towards commercial structures that combine development and usage fees with royalties. Though with greater cyclicality (as royalties recognised based on the amount of chips manufactures and sells), this strategy would allow Synopsys to participate in the production upside once customer chips begin shipping, creating a recurring royalty stream that scales with customers’ chip volumes.

On top of that, Design IP margin recovery could be gradual due to rising costs (R&D) as the Design IP roadmap is rebuilt, with clearer operating leverage from FY2027 as the cost base plateaus and the interface IP pipeline converts. 

Accordingly, we modelled Design IP revenue growth of 6% in FY2026, assuming continued China export restrictions offset the recovery in licensing activity. FY2028 onwards, we expect growth to improve towards low teens as deeper hyperscaler engagements and subsystem adoption scale.

Figure 13: Design IP revenue and operating margin. 

Ansys extends Synopsys from chip design to system-level engineering

While the Ansys acquisition creates near-term earnings drag from financing and integration costs, we believe it meaningfully expands Synopsys’s growth opportunity. As AI accelerators adopt multi-die architectures combining compute chiplets and high-bandwidth memory through 2.5D and 3D advanced packaging, performance is increasingly constrained by thermal behaviour, power integrity, electromagnetic effects and mechanical stress across the wider system.

As such, integrating Ansys’s multiphysics solvers into Synopsys’s EDA workflow allows engineers to analyse these effects earlier, extending Synopsys from silicon design into chip package system codesign, alongside giving Synopsys access to an estimated USD10bn simulation and analysis market, beyond its traditional EDA and IP portfolio, with Ansys simulation analysis EDA revenue growing at approximately 10% annually.

Notably, in 2QFY26, management reported that a leading HPC (high performance computing) customer taped out an advanced AI accelerator using Synopsys’s combined EDA and multiphysics workflow, while Multiphysics Fusion delivered up to three times faster design closure and twice the turnaround speed for complex analogue designs during trials. With commercial rollout beginning in 2HFY26, we expect adoption to broaden as customers bring multiphysics analysis earlier into the chip development process.

Not to mention, Ansys also widens Synopsys’s addressable market, in which its channel network gives Synopsys access to customers it historically did not serve, including engineering organisations across aerospace and defence, automotive and industrial systems. Together with the USD400 million annual cost synergy target, we expect Ansys to support further operating leverage as integration and commercial adoption progress.

Figure 14: Expected realisation of Ansys cost synergies.

Figure 15: After acquisition, Ansys’s simulation & analysis is expected to contribute about 30% of the total revenue.

Table 3: Simulation & Analysis revenue (USD)

	FY2025	FY2026 E	FY2027 E	FY2028 E	FY2029 E
Simulation & Analysis Revenue (USD million)	756.6	2,859.70	3156.1	3426.1	3860.6
Growth y/y (%)		278.0%	10.4%	8.6%	12.7%
Source: Bloomberg Finance L.P., iFAST compilations. Data as of 31 October 2025.

Initiate Coverage with BUY rating

To sum everything up, we believe core EDA remains the main growth engine for Synopsys, while improving Design IP licensing and Ansys cost synergies provide additional operating leverage. On top of that, cross-selling, agentic AI adoption and customised IP royalties remain catalyst for further upsides.

We assigned a fair P/E of 29x (as compared to 30x historical 10-year average forward P/E) to reflects the durability of Synopsys’s EDA earnings and recurring revenue base, while taking a discount for China policy uncertainty and execution risks surrounding the Design IP recovery and Ansys integration. The gap between revenue and EPS growth in FY2026 reflects a full year contribution from Ansys against a partial year FY2025 base (Ansys merger closed in end-July), alongside a higher share count and interest expense from the acquisition, which together dilute the earnings.

Applying that to our forecasting FY2028E adjusted EPS of USD20.83, implying an upside of 50%, with a target price of USD604. Hence, we initiate coverage with a BUY rating.

Table 4: Valuation summary.  

	FY25	FY26 E	FY27 E	FY28 E
Revenue	7054.20	9662.50	10676.08	11798.65
Growth %, y/y	15.1%	37.0%	10.5%	10.5%
EPS	12.91	15.03	17.87	20.83
Growth %, y/y	-2.18%	16.43%	18.87%	16.57%
P/E	64.5	26.87	22.60	19.39
Fair P/E				29
Upside Potential				49.5%
Target Price				604
Source: Bloomberg Finance L.P., iFAST compilations. Data as of 18 August 2026.

Investment Risks

1.      Ansys Integration Execution

Cost synergies are tracking ahead of plan, but full revenue synergy realisation remains multi-year and unproven. Cultural differences between a semiconductor focused and a broad engineering simulation sales force are non-trivial.

2.      China Export Restrictions

China has reset from 16% of revenue in FY2024 to approximately 10–12% in FY2026. Quarterly data shows the softening began before the May 2025 BIS restrictions, suggesting a multi pressure decline rather than a single regulatory event. The primary risk is reimposition of comprehensive restrictions, which would pressure Design IP in particular.

3.      Organic Growth Reacceleration

If AI driven consumption takes longer to flow through the renewal cycle, or if semiconductor R&D spending decelerates from the current elevated pace, organic growth could remain in the mid-to-high single digits.

4.      AI Pricing Dynamics

While we believe AI tools are net revenue accretive through higher consumption per project, productivity gains lead customers to consolidate seats rather than expand usage cannot be fully dismissed. 

Declaration:
This research report was prepared with the assistance of artificial intelligence (AI) tools. iFAST Financial Pte Ltd does not rely exclusively on AI for content generation; the content of this report – including all investment theses, ratings, price targets and conclusions – has been independently reviewed and verified by the research analyst(s) to ensure accuracy and professional integrity.
For specific disclosure, at the time of publication of this report, IFPL (via its connected and associated entities) holds a NIL position in the abovementioned securities. The analyst who produced this report holds a position in Synopsys.