Asian Semiconductors | CXMT's Technical Breakthrough: Will It Reshape the Supply-Demand Balance?

• CXMT's technology path is a reluctant choice driven by equipment constraints; its actual mass-production capability remains behind the Big Three.
• Although the Big Three are expanding aggressively, meaningful new capacity will not start contributing until mid- to late next year.
• AI-driven memory demand is strong, and suppressed demand in smartphones and PCs remains to be released; even with rising supply, the shortage is unlikely to close quickly. CXMT's breakthrough is not enough to change the near-term picture.

CXMT's president said at an industry conference in Shanghai that the company expects to launch a next-generation DDR5 RDIMM server memory built on a 4F² architecture by the end of 2026. The news drew an intense market reaction; coming on top of existing doubts about the financing and returns of artificial intelligence investment, it added further pressure to the market. Measured from June's highs, the share prices of SK hynix and Samsung Electronics have already fallen sharply. Is CXMT's technology breakthrough enough to change the near-term supply-demand balance? Has the share-price reaction been excessive? Or have the market's doubts about AI investment already begun to materially affect corporate business prospects?

Understanding the density limit from the DRAM cell

To understand CXMT's latest technology progress, we may need to dig into the fundamentals of DRAM architecture.

Each DRAM memory cell consists of a capacitor and a transistor: the capacitor stores charge, and different charge states represent 0 or 1. But a chip contains a huge number of memory cells, so how does the circuitry find the data it needs? Think of storage as a spreadsheet: each square is a memory cell, and wordlines and bitlines form the squares, like the X and Y axes, letting the circuitry locate data through addresses in two directions.

So each square not only has to store data; it also has to support addressing. How these parts are arranged determines how much planar area each memory cell occupies. Engineers keep trying different methods, hoping to fit more bits into the limited area of a wafer.

Figure 1: Conventional memory design and architecture

There are two technology routes:

1. Shrink the components: keep the existing layout and make the components and interconnects smaller, equivalent to drawing the same picture with a finer pen.
2. Change the layout: without shrinking the existing components, rearrange how the different parts are arranged and positioned so that they take up less area. CXMT's technology breakthrough falls into this category.

Equipment constraints: why CXMT stands the transistor up

The first route requires making components and interconnects finer, and that calls for EUV. EUV is like a finer pencil, helping to draw more precise patterns. CXMT cannot obtain such equipment; it can still keep scaling down using DUV with multi-patterning, but the number of manufacturing steps and the cost both rise. Equipment constraints pushed it to start from design earlier, taking the second route.

How does rearranging save space? Returning to the spreadsheet analogy, each square has to hold a capacitor, a transistor and a contact. If components originally arranged laterally are instead arranged vertically, the planar area the square occupies falls. The vertical structure CXMT is pursuing stands the transistor up, so that the bitline, the transistor and the capacitor connect along the vertical direction. That way, even without making each component smaller, the whole memory cell takes up a little less space.

Figure 2: CXMT's vertical DRAM architecture

Raising density still means clearing three mass-production hurdles

Designing the transistor vertically saves planar area, but it still has to face the following three challenges:

1. Yield: vertical components and contacts must be manufactured precisely, and the bonding must be reliable. If the number of defects in manufacturing rises, occupying less space per memory cell does not necessarily mean more usable output.
2. Cost: the additional manufacturing, bonding and testing steps may offset the gains that higher density brings. Being able to store more data on each chip does not mean the cost per bit is already lower.
3. Customer qualification: beyond reading and writing correctly, the chip must also prove that it is reliable in long-term use and can be delivered consistently and steadily before customers adopt it in volume. CXMT needs domestic customers willing to help with testing and improvement, which could speed up adoption of a new product, but validation is still required.

So the announcement of the new architecture sets out CXMT's direction for raising density, but discloses nothing about yields, cost or customer adoption. The information available today still cannot show the technology's actual progress or its impact on the industry.

Technology routes and supply: four players on different paths

CXMT has not released a revolutionary technology this time, yet the market still fears China's manufacturing capability, believing it is likely to dump large volumes of cheap DRAM onto the global market and bring this memory boom to an end. Our research finds that this argument does not stand up to scrutiny at all. To test the claim, we can examine each of the four players' process progress, next-generation direction, yield evidence and capacity plans one by one.

·         Samsung: The first in the industry to use 1c process

Samsung claims to be among the first in the industry to use its 1c process for commercial HBM4 production; the next-generation HBM4E sample uses 1c together with its in-house 4nm logic process to make the base die.

On next-generation cell structure, Samsung's product direction is the same as CXMT's, aiming to adopt a new cell architecture, but this remains a research-stage result.

On supply and demand, management's view appears highly optimistic, running against the market's recent worries: Kim Jaejune, Executive Vice President of its Memory Business, predicted at the second-quarter earnings call that global memory supply constraints will be more severe in 2027, and expects the shortage to extend into 2028.

On capacity, almost all of its incremental capacity comes from Pyeongtaek PT4 and PT5, with the two lines rising from a combined 153k wafers per month at end-2026 to 330k at end-2028; its other lines dip slightly in 2027 and recover in 2028, for a combined increase of only about 3% over the two years.

Table 1: Samsung's main DRAM fabs and monthly wafer starts

Fab	End-2026	End-2027	End-2028
Hwaseong 15	153	134	155
Hwaseong 16	67	54	65
Hwaseong 17	86	75	90
Pyeongtaek PT1	91	80	95
Pyeongtaek PT2	96	84	100
Pyeongtaek PT3	96	84	100
Pyeongtaek PT4	134	176	210
Pyeongtaek PT5	0	30	90
Total	723	717	905
Source: Company data, market research and iFAST Compilations. Unit: thousand wafers per month. Data as of 14 October 2026

·         SK hynix: moving to 1c, with the yield trade-off stated most clearly

SK hynix is also positioning itself actively in the 1c process. But as the process shrinks, SK hynix appears to face declining yields. On next-generation cell structure, it also points to a new cell architecture, the same direction as Samsung and CXMT, but still at the research stage.

On capacity planning, the increment comes mainly from Cheongju M15X and Yongin Y1, with the two fabs rising from a combined 65k wafers per month at end-2026 to 170k at end-2028; its other four fabs increase only 13% over the same period. Company-wide, capacity rises from 590k to 770k wafers.

Table 2: SK hynix's main DRAM fabs and monthly wafer starts

Fab	End-2026	End-2027	End-2028
Wuxi 1	102	107	122
Wuxi 2	93	97	105
Cheongju M14	162	155	177
Cheongju M16	172	170	194
Cheongju M15X	19	83	94
Yongin Y1	5	50	80
Total	553	662	772
Source: Company data, market research and iFAST Compilations. Unit: thousand wafers per month. Data as of 14 October 2026

·         Micron: already at production scale, with growth coming from node migration

Micron's mainstay is its 1γ process, which produces more than 30% more bits per wafer than the previous 1β generation. On capacity, the increment comes from Idaho ID1 and Tongluo in Taiwan, with first wafer output expected in mid-2027; existing fabs also grow modestly through 2028.

Table 3: Micron's main DRAM fabs and monthly wafer starts

Fab	End-2026	End-2027	End-2028
Fab 4 (Manassas)	16	17	22
Fab 15 (Hiroshima 1)	57	63	78
Fab 16 (Powerchip)	63	70	87
Fab 11 (Inotera)	57	63	78
Fab 1 + 2 (Taiwan)	57	63	78
Idaho ID1	0	30	90
Tongluo (PSMC P5)	8	40	52
Total	258	346	485
Source: Company data, market research firms and iFAST Compilations. Unit: thousand wafers per month. Data as of 14 October 2026

·         CXMT: equipment-constrained, with density coming from a reworked structure

CXMT had already announced its fifth-generation DRAM platform, G5, and volume production of the related LPDDR5X. Without access to EUV, the room to keep shrinking the process is limited, so changing the memory cell structure has become the main route to higher density.

As noted above, the new structure's yield, customer qualification and shipment volumes remain unconfirmed. More importantly, we believe CXMT's output is not even sufficient to meet the needs of major domestic customers, its manufacturing cost is about 30% higher than the big three, and prices for comparable server modules are no lower than theirs. The idea that its products could flood the world with cheap DRAM in a short time and bring this boom to an end is simply nonsense.

Table 4: Technology routes and supply comparison of the four players

Item	Samsung	SK Hynix	Micron	CXMT
Current mainstream node	1c (6th-generation 10nm-class)	1c	1γ	G5
Disclosed volume production	1c in commercial production for HBM4	1c products shipping at scale from 2Q 2026	1γ the largest production node	G5 and LPDDR5X in volume production
Next-generation direction	4F² test chip completes read/write	4F² vertical gate research	Next node in volume production in 2H calendar 2027	4F² DDR5 RDIMM launched by end-2026
Yield and delivery evidence	Company says HBM4 yields are stable; 4F² remains experimental	Engineers publicly explain the scaling-versus-yield trade-off	Main node already at production scale	New structure still ramping and awaiting delivery
Source: Company data, conference papers, TrendForce and iFAST Compilations. Data as of 14 October 2026

Industry supply and demand: can supply growth keep up with demand?

The monthly wafer capacity of Samsung, SK hynix and Micron is expected to rise from about 1.53 million wafers at end-2026 to about 2.16 million at end-2028, a two-year compound growth rate of about 19%. Combining capacity expansion and process progress, and taking into account the wafer capacity absorbed by HBM production, we estimate that DRAM bit supply will grow by about 20% a year over the next two years.

Three factors are driving demand:

1. Model parameters keep growing: one report notes that Moonshot AI is developing a model with 5 trillion to 6 trillion parameters, close to twice the scale of Kimi K3, released this July; the scale of US frontier models is expanding as well.
2. Contexts keep getting longer: a 1-million-token long context is now fairly common, and we expect the window to keep widening as more applications adopt it.
3. Rising enterprise and consumer penetration: OpenAI's and Anthropic's revenue continues to grow on a high base, and Meta's Muse topped the free app charts in the US and Canada within two weeks of launch, with downloads surpassing ChatGPT's over the comparable period. AI adoption is clearly accelerating for both individuals and enterprises.

These factors support continued growth in memory demand. We assume demand will rise by about 25% a year over the next two years, above our baseline estimate of about 20% supply growth a year, meaning the new supply may not be enough to eliminate the shortage. We are not alone in saying this: Micron has also pointed out that tight supply has already limited how fast customers can increase their configurations — the configuration growth we see today is itself an already-suppressed result. Smartphones and PCs face the same pressure from rising component prices, with some demand currently held back. This pent-up demand is likely to return as supply improves and prices moderate, meaning higher supply does not by itself close the shortage.

How do long-term purchase agreements change the memory cycle?

Beyond spot prices, the long-term agreements (LTAs) that suppliers sign with customers are also an important part of judging future supply, demand and earnings. The market used to worry that the memory industry is highly cyclical: rising prices spur capacity expansion, and the new supply can later create a glut, pulling prices and earnings back down, so investors have generally been reluctant to award higher valuations. Now the major manufacturers are signing long-term agreements with customers, an arrangement that may reduce the industry's earnings volatility.

These contracts redistribute risk between the two sides mainly through three types of clause:

1.     Price floors protect suppliers. Micron says that even if prices fall to the contractual floor, gross margin would still be “far above the peak of any previous cycle”; Samsung also confirms that its LTA price floors are set at a level “sufficient to offset future investment risk”. Such clauses reduce the impact of falling prices on earnings and investment returns.

2.     Minimum purchase commitments. Many agreements use take-or-pay arrangements. At Micron, for example, 26 contracts carry customer financial commitments of USD 32 billion; the company received USD 12.3 billion of cash deposits in the quarter, and held USD 12.7 billion of deposits on its books at quarter-end. Customers must meet minimum purchase volumes before they can reclaim their deposits in the second half of the contract. Samsung's prepayments also rose 70% in the first half of this year, to KRW 4.47 trillion. These arrangements improve suppliers' visibility on future orders and cash flow.

3.     Price ceilings protect customers. Several of Micron's largest contracts lock the prices of existing products at the market level of the second quarter of 2026; once all the relevant contracts are signed, they are expected to cover about 40% of revenue. Through LTAs, suppliers give up part of the price upside in exchange for more predictable orders, earnings and prepayments to support their expansion plans. This helps lower investment risk, but investors should note that LTAs do not mean the memory industry's cyclicality has disappeared.

The coverage of long-term agreements is still limited. LTAs are estimated to account for only 20% to 30% of the big three memory makers' DRAM shipments in 2027, and new products such as LPDDR6 and DDR6 also fall outside the coverage of existing LTAs. As for price-sensitive consumer electronics such as smartphones and PCs, their memory is still largely purchased at market prices. This arrangement is a double-edged sword: on one hand, the price ceilings do not fully cap suppliers' earnings upside; on the other, LTAs protect only part of the business, and most shipments still have to bear price-decline risk if supply and demand turn.

HBM's contractual arrangements differ from ordinary DRAM: contracts lock in purchase volumes in advance, while prices are renegotiated every year. HBM4 prices in 2027 are expected to rise from about USD 2 per Gb to USD 4–5. This model both improves the visibility of demand and preserves suppliers' room to adjust prices in response to market supply and demand and product upgrades.

TSMC: results stay strong, with capacity expansion answering AI demand

Much of the above has been devoted to analysing memory technology and shifts in supply and demand, but the investment opportunities in Asian semiconductors certainly do not stop at memory; they also include the industry's backbone, TSMC. The company reported third-quarter results on 15 October, with revenue and earnings extending strong growth, and its fourth-quarter guidance also points to further revenue gains. At a time when the market is worried about the financing and returns of AI investment, TSMC's actual results and management's outlook provide another important basis for judging the earnings prospects of Asian semiconductors.

Third-quarter revenue reached NT$1.494 trillion, up 50.9% year-on-year; net income reached NT$763.1 billion, up 68.7% year-on-year. In US dollar terms, revenue was USD 46.72 billion, above the previous guidance ceiling of USD 45.8 billion. Although gross margin fell quarter-on-quarter under the cost of the initial 2nm ramp, it was still 6.9 percentage points higher than a year earlier, and operating income rose 75.0% year-on-year, reflecting the continued strength of core business profitability.

Table 5: TSMC's key third-quarter results and fourth-quarter guidance

Metric	3Q 2026 actual	YoY change	4Q 2026 guidance
Revenue (USD billion)	46.72	+41.2%	52.3–54.3
Net income (NT$ billion)	763.1	+68.7%	—
EPS (NT$)	29.43	+68.7%	—
Gross margin	66.4%	+6.9 ppt	65%–67%
Operating margin	58.7%	+8.1 ppt	56.5%–58.5%
Source: TSMC and iFAST Compilations. Data as of 15 October 2026

More noteworthy still, the midpoint of the fourth-quarter revenue guidance is USD 53.3 billion, up about 14% again from the third quarter. On the earnings call, management said AI demand is extremely strong and shows no sign of slowing; the adoption of AI agents and the spread of open-source models help lower the barrier to use, driving more demand for advanced process technology, while demand for CPU and networking chips is also rising.

On capital expenditure. TSMC is maintaining its 2026 capex budget of USD 60 billion to 64 billion, and expects capex from 2026 to 2028 to be significantly higher than in the preceding three years. This continued investment in capacity reflects management deploying capacity in line with customers' multi-year product plans, with the supply-demand gap it currently assesses still fairly wide.

TSMC also confirmed that its capacity planning already takes cloud service providers' capex, financing, power and other component supply into account, and that it has sent teams to verify the construction progress and power supply of US data centres. Management acknowledges that consumer and price-sensitive markets are still affected by rising component prices and macro uncertainty, and so remains cautious about its 2027 plans, but demand for advanced process technology remains extremely strong.

Investment implications: earnings still strong, and a more attractive valuation after the pullback

In sum, CXMT's technology progress is worth watching, but going from a new architecture to cost-competitive large-scale delivery still has to clear hurdles in yield, cost and customer qualification, and at this stage is not enough to change our positive view on near-term memory supply and demand. TSMC's latest results and fourth-quarter guidance also show that advanced-process demand remains strong. Memory supply and demand, the earnings protection that LTAs provide, and TSMC's growth outlook together support the earnings prospects of the leading Asian semiconductor companies. With earnings growth staying strong while share prices have pulled back on market volatility, the forward P/E of the FactSet Asia Semiconductor Index has now fallen well beyond one standard deviation below the mean, and we consider Asian semiconductors highly attractive at this stage.

Investors who wish to participate in these opportunities could consider deploying through the Global X Asia Semiconductor ETF (3119), which tracks the FactSet Asia Semiconductor Index; based on a fair P/E of 20x, the potential upside is 158.6%.

Figure 3: FactSet Asia Semiconductor Index and forward P/E

Table 6: FactSet Asia Semiconductor Index valuation

FactSet Asia Semiconductor Index	2025A	2026E	2027E	2028E
EPS (HKD)	19.26	67.60	88.09	97.37
Earnings growth	—	251.0%	30.3%	10.5%
Fair value (at a 20x P/E)	—	—	—	1,947
Upside potential	—	—	—	158.6%
Source: Bloomberg and iFAST Compilations. Data as of 16 October 2026